In recent years, in the through silicon via technology, there has been desired a technique of filling a metal into a minute space provided on a semiconductor wafer. Because the through silicon via technology makes it possible to develop a chip stacking technology using through hole electrode, it is expected that a high-performance and high-speed semiconductor system is achieved by a three-dimensional stacked integrated circuit. In order to secure stable conduction in a through silicon via, it is required to perform metal filling with high yield without any defects such as a crack and a void.
Conventionally, as a technique of filling a metal into a minute space on a semiconductor wafer, besides copper plating methods and dipping methods in which a semiconductor wafer is immersed in a molten metal tank, there is suggested, as shown in the Patent documents 1 and 2, a melting and vacuum-sucking method in which, in a pressure-reduced chamber, a metal body for filling is arranged on a surface of a sample, where a minute space to be filled with a metal is formed, so that the metal body for filling covers the minute space, and the metal body for filling is heated and melted, and then the inside of the vacuum chamber is pressurized to a pressure equal to or greater than atmospheric pressure by an inert gas, thereby causing the molten metal to be vacuum-sucked into the minute space.